Device Variability Impact on Logic Gate Failure Rates

Well-established reliability models indicate that the failure rates of scaled CMOS will continue to increase due to manufacturing variability and wear-out caused by negative bias temperature instability and hot carrier injection effects. Thus, the reliability of future devices is a critical concern for circuit designers. In order to predict the feasibility and reduce the cost of these new, fault-prone structures, techniques to efficiently determine circuit reliability are needed. To this end, we have previously introduced a probabilistic gate-level model based on stuck-at and inversion faults to evaluate circuit reliability and derive fundamental error bounds for logic gates. In this paper, we utilize recent work on transistor variability in emerging silicon devices to confirm the validity of these fault models as well as to determine realistic fault rates. We show that the failure mechanisms and error rates that we derive can be incorporated into our PGM framework, and therefore, our method of reliability analysis can potentially be used in the design and manufacturing of circuits to reduce testing time and indicate the need for fault mitigation techniques.